Javalab [Javalab] Lars Drud Nielsen
ldn@oersted.dtu.dk

npn Transistor biasing

The circuit is a general bias circuit for a common-emitter (CE) npn amplifier stage, based on a single positive voltage supply.

The transistor is described by a simple model with fixed parameters VBEdiode = 0.6 V, VCEsat = 0.2 V, RCEsat = 50 W (Wakerly: Digital Design, 2nd ed., sec. 3.9.3). The current gain b of the transistor is adjustable. The horizontal resistor in the base lead is not a part of the bias circuit, but represents a refinement of the transistor model by addition of a non-zero series resistance of the base-emitter diode.

AC operation of the amplifier stage is imagined to take place under the following conditions, not affecting the biasing considerations: The emitter resistor is shorted by a bypass capacitor. AC input voltage is coupled to the base node through a another large capacitor, and otput voltage is coupled from the collector node via a third large capacitor.

The comments at the bottom of the diagram may help you to optimize the bias circuit. With the transistor biased into its active region Av is the resulting ac voltage gain, Rin and Rout are the input and output ac resistances of the amplifier stage. Furthermore, the maximum output voltage amplitude Vout is indicated (as limited by either saturation or cut off). Finally, P is the total power from the supply with no ac signals applied.

Optimization may be carried out with several regards: High gain, low power consumption, large output voltage swing, low supply voltage, low influence of variations in transistor parameters, etc., etc.

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