Difference between revisions of "STM32F107VC/Bit-banding"
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=Problem= | =Problem= | ||
WHen writing to memory addresses that are shared with multiple processes/tasks - the normal Read-Modify-Write solution can cause problems if another task i scheduled to run before the Read-Modify-Write cycle is finished and the new task makes its own Read-Modify-Write on the same shared address. | WHen writing to memory addresses that are shared with multiple processes/tasks - the normal Read-Modify-Write solution can cause problems if another task i scheduled to run before the Read-Modify-Write cycle is finished and the new task makes its own Read-Modify-Write on the same shared address. | ||
| Line 19: | Line 20: | ||
|+ Example of problem. | |+ Example of problem. | ||
|- bgcolor=lightgrey | |- bgcolor=lightgrey | ||
| − | ! | + | ! Step !! Operation !! Task value !!TER at 0x4001 !! Action |
|- | |- | ||
| − | | Task A Reads | + | | 0 || || || align=center| 0000 0000 || |
| − | |- align=center | + | |- |
| + | | 1 ||Task A Reads TER ||align=center| 0000 0000 ||align=center| 0000 0000 || | ||
| + | |- | ||
| + | | 2 ||RTOS task switch to Task B ||align=center| 0000 0000 ||align=center| 0000 0000 || | ||
| + | |- | ||
| + | | 3 ||Task B Reads TER ||align=center| 0000 0000 ||align=center| 0000 0000 || | ||
| + | |- | ||
| + | | 4 ||Task B Modify read Value to start Timer 2 ||align=center| 0000 0100 ||align=center| 0000 0000 || | ||
| + | |- | ||
| + | | 5 || Task B Write TER ||align=center| 0000 0100 ||align=center| 0000 0100 || Timer 2 start | ||
| + | |- | ||
| + | | 6 || RTOS task switch to Task A ||align=center| 0000 0000 ||align=center| 0000 0000 || | ||
| + | |- | ||
| + | | 7 ||Task A Modify read Value to start Timer 1 ||align=center| 0000 0010 ||align=center| 0000 0100 || | ||
| + | |- | ||
| + | | 8 || Task A Write TER ||align=center| 0000 0010 ||align=center| 0000 0010 || Timer 1 start and '''Timer 2 Stop unattentional''' | ||
| + | |- | ||
|} | |} | ||
| + | =Avoiding= | ||
| + | In systems without Bit Banding or Atomic Bit Manipulation it's necessary to disable interrupt during the '''Read-Modify-Write''' operation when accessing shared resources. | ||
| + | |||
| + | [[Category:ARM]][[Category: STM32F107VC]] | ||
Latest revision as of 11:43, 29 January 2012
This article is under development....
Problem
WHen writing to memory addresses that are shared with multiple processes/tasks - the normal Read-Modify-Write solution can cause problems if another task i scheduled to run before the Read-Modify-Write cycle is finished and the new task makes its own Read-Modify-Write on the same shared address.
This problem could occur in the configuration Registers of Peripheral - fx. Timers, Interrupt Controllers.
Example
The Timer Enable Register (TER) at address 0x4001 is used to enable Timer 1 and Timer 2.
| bit 7 | bit 6 | bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
|---|---|---|---|---|---|---|---|
| X | X | X | X | X | 1 = Enable Timer 2 0 = Disable Timer 2 |
1 = Enable Timer 1 0 = Disable Timer 1 |
X |
Timer 1 is used by Task A and Timer 2 is used by Task B.
| Step | Operation | Task value | TER at 0x4001 | Action |
|---|---|---|---|---|
| 0 | 0000 0000 | |||
| 1 | Task A Reads TER | 0000 0000 | 0000 0000 | |
| 2 | RTOS task switch to Task B | 0000 0000 | 0000 0000 | |
| 3 | Task B Reads TER | 0000 0000 | 0000 0000 | |
| 4 | Task B Modify read Value to start Timer 2 | 0000 0100 | 0000 0000 | |
| 5 | Task B Write TER | 0000 0100 | 0000 0100 | Timer 2 start |
| 6 | RTOS task switch to Task A | 0000 0000 | 0000 0000 | |
| 7 | Task A Modify read Value to start Timer 1 | 0000 0010 | 0000 0100 | |
| 8 | Task A Write TER | 0000 0010 | 0000 0010 | Timer 1 start and Timer 2 Stop unattentional |
Avoiding
In systems without Bit Banding or Atomic Bit Manipulation it's necessary to disable interrupt during the Read-Modify-Write operation when accessing shared resources.