Difference between revisions of "STM32F107VC/GPIO"
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|+ GPIO Configuration Registers. | |+ GPIO Configuration Registers. | ||
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| − | ! Name !! Function | + | ! Name !! [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf Section] !! Function |
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| − | | | + | |[[/GPIO'''x'''_CRL|GPIO'''x'''_CRL]] || align=center | 9.2.1 || Port configuration register low ('''x''' = Port A to G ) |
|- | |- | ||
| − | | | + | |[[/GPIO'''x'''_CRH|GPIO'''x'''_CRH]] || align=center | 9.2.2 || Port configuration register high ('''x''' = Port A to G ) |
| + | |- | ||
| + | |[[/GPIO'''x'''_IDR|GPIO'''x'''_IDR]] || align=center | 9.2.3 || port input data register ('''x''' = Port A to G ) | ||
| + | |- | ||
| + | |[[/GPIO'''x'''_ODR|GPIO'''x'''_ODR]] || align=center | 9.2.4 || port output data register ('''x''' = Port A to G ) | ||
| + | |- | ||
| + | |[[/GPIO'''x'''_BSRR|GPIO'''x'''_BSRR]] || align=center | 9.2.5 || Port bit set/reset register ('''x''' = Port A to G ) | ||
| + | |- | ||
| + | |[[/GPIO'''x'''_BRR|GPIO'''x'''_BRR]] || align=center | 9.2.6 || Port bit reset register ('''x''' = Port A to G ) | ||
| + | |- | ||
| + | |[[/GPIO'''x'''_LCKR|GPIO'''x'''_LCKR]] || align=center | 9.2.7 || Port configuration lock register ('''x''' = Port A to G ) | ||
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Revision as of 09:44, 28 August 2011
General Purpose and Alternate Function I/O
GPIO functional description
Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes:
- Input floating
- Input pull-up
- Input-pull-down
- Analog
- Output open-drain
- Output push-pull
- Alternate function push-pull
- Alternate function open-drain
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access.
Default configuration
During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode.
Port Bit Configuration
Each bit can be configured using the configuration registers shown below
| Name | Section | Function |
|---|---|---|
| GPIOx_CRL | 9.2.1 | Port configuration register low (x = Port A to G ) |
| GPIOx_CRH | 9.2.2 | Port configuration register high (x = Port A to G ) |
| GPIOx_IDR | 9.2.3 | port input data register (x = Port A to G ) |
| GPIOx_ODR | 9.2.4 | port output data register (x = Port A to G ) |
| GPIOx_BSRR | 9.2.5 | Port bit set/reset register (x = Port A to G ) |
| GPIOx_BRR | 9.2.6 | Port bit reset register (x = Port A to G ) |
| GPIOx_LCKR | 9.2.7 | Port configuration lock register (x = Port A to G ) |
| Configuration mode | CNF1 | CNF0 | MODE1 | MODE0 | PxODR register | |
|---|---|---|---|---|---|---|
| General Purpose Output | Push-Pull | 0 | 0 | 01 10 11 See Mode below |
0 or 1 | |
| Open Drain | 1 | 0 or 1 | ||||
| Alternate function Output | Push-Pull | 1 | 0 | Don't Care | ||
| Open Drain | 1 | Don't Care | ||||
| Input | Analog | 0 | 0 | 00 | Don't Care | |
| Input Floating | 1 | Don't Care | ||||
| Input Pull-Down | 1 | 0 | 0 | |||
| Input Pull-Up | 1 | |||||
| MODE[1:0] | Meaning |
|---|---|
| 00 | Reserved |
| 01 | Max. output speed 10 MHz |
| 10 | Max. output speed 2 MHz |
| 11 | Max. output speed 50 MHz |
Detailed description
For detailed description of GPIO see STM32F107VC Reference Manual Chapter 9.