Difference between revisions of "FPGA"
From Teknologisk videncenter
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**[[Media:QuartusII_HurtigGuide-1-.pdf|QuartusII Quickguide]] (Loads PDF file) | **[[Media:QuartusII_HurtigGuide-1-.pdf|QuartusII Quickguide]] (Loads PDF file) | ||
**[[Media:Start_af_nyt_Schematic_projekt_i_Quartus_II-1-.pdf|QuartusII Schematic projekt start]] (Loads PDF file) | **[[Media:Start_af_nyt_Schematic_projekt_i_Quartus_II-1-.pdf|QuartusII Schematic projekt start]] (Loads PDF file) | ||
| − | **[[Media:Start_af_nyt_VHDL_projekt_i_Quartus_II.pdf|Quartus VHDL projekt start]] (Loads PDF file) | + | **[[Media:Start_af_nyt_VHDL_projekt_i_Quartus_II-1-.pdf|Quartus VHDL projekt start]] (Loads PDF file) |
| − | **[[Media:Samlet_schmatic_%26_vhdl.pdf|Schamtic & VHDL]] (Loads PDF file) | + | **[[Media:Samlet_schmatic_%26_vhdl-1-.pdf|Schamtic & VHDL]] (Loads PDF file) |
**[[Media:VHDL.pdf|VHDL]] (Loads PDF file) | **[[Media:VHDL.pdf|VHDL]] (Loads PDF file) | ||
*Lkaa vejledning | *Lkaa vejledning | ||
Revision as of 09:24, 7 September 2010
- Teori
- Ole vildledninger???
- QuartusII Quickguide (Loads PDF file)
- QuartusII Schematic projekt start (Loads PDF file)
- Quartus VHDL projekt start (Loads PDF file)
- Schamtic & VHDL (Loads PDF file)
- VHDL (Loads PDF file)
- Lkaa vejledning
- Hints
- Installation af driver til DE1 board: Vælg denne sti: C:\altera\91\quartus\drivers\usb-blaster
- Eller hente driver fra Altera's hjemmeside samt instruktion: http://www.altera.com/support/software/drivers/dri-index.html
- Clk_divider fra 27MHz til 100Hz (Loads ZIP file)
- Tidsmåler!! uden logik og med 100Hz clk (Loads ZIP file)
- Digitak logik (Loads ZIP file)
I have one method of using a counter. The formula for calculating the counter is ( Actual Frequency / required frequency)
use that as the set point for your counter and make use of this code(This IS for 26MHz from 100MHz clock, so the Count value WilL be(100m/26M = 3.)
- if (clock = '1' and clock'event ) then
- if ( count /= 4)
- count := count + 1 ;
- clock_out := clock_out ;
- else
- count := 0 ;
- clock_out := not clock_out ;
- end if;
- end if ;
so for 13MHz the count value will be 7
- Opgaver
- FPGA øvelser (Loads PDF file)
- Links