Difference between revisions of "STM32F107VC/Interrupts and Events"
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=Nested vectored interrupt controller (NVIC)= | =Nested vectored interrupt controller (NVIC)= | ||
| − | *See the | + | *See the [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf Reference manual] Chapter 10. Remember the [[STM32F107VC]] is a ''connectivity line device''. |
| − | *See the | + | *See the [http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00228163.pdf STM32F10xxx/20/21/L1 Cortex-M3 programming manual] Section 4.3 for programming information. (See section 4.3.10 NVIC Design hints and Tips) |
=Features= | =Features= | ||
*68 (not including the sixteen Cortex™-M3 interrupt lines) | *68 (not including the sixteen Cortex™-M3 interrupt lines) | ||
Revision as of 05:34, 12 September 2011
Nested vectored interrupt controller (NVIC)
- See the Reference manual Chapter 10. Remember the STM32F107VC is a connectivity line device.
- See the STM32F10xxx/20/21/L1 Cortex-M3 programming manual Section 4.3 for programming information. (See section 4.3.10 NVIC Design hints and Tips)
Features
- 68 (not including the sixteen Cortex™-M3 interrupt lines)
- 16 programmable priority levels (4 bits of interrupt priority are used)
- Low-latency exception and interrupt handling
- Power management control
- Implementation of System Control Registers
Example using USART2 interrupt
From the [Reference manual] table 61 in section 10.1.2 its seen that
- USART2 global interrupt
- Position: 28
- Priority: 45 - Settable
- Address: 0x0000_00D8