Difference between revisions of "STM32F107VC/Using the RTC Real Time Clock"

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m (→‎Enabling the RTC)
m (→‎Enabling the RTC)
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Preparing for programming the STM32F107VC Real Time Clock.
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<p>Preparing for programming the STM32F107VC Real Time Clock.
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<source lang=c>
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<span class="fck_mw_source" _fck_mw_customtag="true" _fck_mw_tagname="source" lang="c">fckLR//Define where in the memory the RTC start address peripheral is locatedfckLR#define RTC_BASE        0x40002800 // See reference manual page 52fckLRfckLR//Define the RTC register map. See reference manual section 18.4.7 page 474fckLRunsigned short int volatile * const rtc_crh  = (unsigned short int *) RTC_BASE + 0x0;fckLRunsigned short int volatile * const rtc_crl  = (unsigned short int *) RTC_BASE + 0x4;fckLRunsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;fckLRfckLR//Initialize the RTC peripheral. See reference manual section 18 page 463fckLRvoid rtc_init(void) {fckLR // Your code herefckLR}fckLR</span>
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//Define where in the memory the RTC start address peripheral is located
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</p>
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#define RTC_BASE        0x40002800 // See reference manual page 52
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<h1>Initializing the RTC</h1>
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<dl><dt>Goals
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//Define the RTC register map. See reference manual section 18.4.7 page 474
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</dt><dd>Enabling the RTC
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unsigned short int volatile * const rtc_crh  = (unsigned short int *) RTC_BASE + 0x0;
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</dd><dd>One seconds TICK
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unsigned short int volatile * const rtc_crl  = (unsigned short int *) RTC_BASE + 0x4;
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</dd><dd>No interrupts enable
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unsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;
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</dd><dd>Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
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</dd><dd>Using external XTAL
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//Initialize the RTC peripheral. See reference manual section 18 page 463
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</dd><dd>Write protect against accidental writes
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void rtc_init(void) {
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</dd></dl>
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// Your code here
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<h2> Enabling the RTC </h2>
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}
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<h3>Power on Init</h3>
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</source>
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<ol><li>To enable the RTC it is necessary to enable the Power interface in the RCC-&gt;APB1ENR register by setting the PWREN bit to 1. <span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 8.3.8 page 144</span>  
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=Initializing the RTC=
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</li><li>To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR-&gt;CR register set PLS[2:0] to 011<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref" name="CR">Reference manual section 5.4.1 page 75</span>  
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;Goals
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</li><li>To enable the <i>Power voltage detector</i> in the PWR-&gt;CR register set PVDE to 1.<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 5.4.1 page 75</span>
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:Enabling the RTC
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</li></ol>
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:One seconds TICK
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<h3>Checking if RTC running</h3>
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:No interrupts enable
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<ol><li>In the RCC-&gt;BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref" name="BDCR">Reference manual section 8.3.9 page 146</span>
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:Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
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</li></ol>
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:Using external XTAL
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<h3>Programming the RTC</h3>
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:Write protect against accidental writes
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<ol><li>To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 1. <span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref" name="CR"></span>  
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== Enabling the RTC ==
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</li><li>To select LSE (Low Speed External XTAL) as clocksource in the RCC-&gt;BDCR register bits RTCSEL[1:0] = 01 <span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref" name="BDCR">Reference manual section 8.3.9 page 146</span>  
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===Power on Init===
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</li><li>To turn on the LSE in the RCC-&gt;BDCR register bit LSEON = 1.<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 8.3.9 page 146</span>  
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#To enable the RTC it is necessary to enable the Power interface in the RCC-&gt;APB1ENR register by setting the PWREN bit to 1. <ref>Reference manual section 8.3.8 page 144</ref>  
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</li><li>Wait in while loop (timed out for error check) for the LSE to be ready in RCC-&gt;BDCR register bit LSERDY.<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 8.3.9 page 146</span>  
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#To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011<ref name="CR">Reference manual section 5.4.1 page 75</ref>  
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</li><li>Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC-&gt;PRLH = 0 and RTC-&gt;PRLL = 0x7fff.<span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref"> Reference manual section  18.4.3 page 470</span>  
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#To enable the ''Power voltage detector'' in the PWR-&gt;CR register set PVDE to 1.<ref>Reference manual section 5.4.1 page 75</ref>  
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</li><li>Setting the Counter to the current time in seconds since epoch. (Set the RTC-&gt;CNTH before the RTC-&gt;CNTL avoiding RTC-&gt;CNTL = 0xffff incrementing RTC-&gt;CNTH before writing to it.) <span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 18.4.5 page 472</span>  
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===Checking if RTC running===
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</li><li>To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 0. <span class="fck_mw_ref" _fck_mw_customtag="true" _fck_mw_tagname="ref">Reference manual section 5.4.1 page 75</span>
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#In the RCC->BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)<ref name="BDCR">Reference manual section 8.3.9 page 146</ref>  
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</li></ol>
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===Programming the RTC===
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<h1>Links</h1>
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#To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 1. <ref name="CR"></ref>  
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<ul><li><a _fcknotitle="true" href="Const and volatile type qualifiers">Const and volatile type qualifiers</a>
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#To select LSE (Low Speed External XTAL) as clocksource in the RCC-&gt;BDCR register bits RTCSEL[1:0] = 01 <ref name=BDCR>Reference manual section 8.3.9 page 146</ref>  
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</li></ul>
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#To turn on the LSE in the RCC-&gt;BDCR register bit LSEON = 1.<ref>Reference manual section 8.3.9 page 146</ref>  
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<h1>References</h1>
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#Wait in while loop (timed out for error check) for the LSE to be ready in RCC-&gt;BDCR register bit LSERDY.<ref>Reference manual section 8.3.9 page 146</ref>  
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<p><span class="fck_mw_references" _fck_mw_customtag="true" _fck_mw_tagname="references" />
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#Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC-&gt;PRLH = 0 and RTC-&gt;PRLL = 0x7fff.<ref> Reference manual section  18.4.3 page 470</ref>  
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</p><a _fcknotitle="true" href="Category:STM32F107VC">STM32F107VC</a> <a _fcknotitle="true" href="Category:ARM">ARM</a>
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#Setting the Counter to the current time in seconds since epoch. (Set the RTC-&gt;CNTH before the RTC-&gt;CNTL avoiding RTC-&gt;CNTL = 0xffff incrementing RTC-&gt;CNTH before writing to it.) <ref>Reference manual section 18.4.5 page 472</ref>  
 
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#To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR-&gt;CR register setting the DBP bit to 0. <ref>Reference manual section 5.4.1 page 75</ref>
 
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=Links=
 
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*[[Const and volatile type qualifiers]]
 
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=References=
 
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<references/>
 
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[[category:STM32F107VC]][[Category:ARM]]
 

Revision as of 09:26, 7 March 2012

Preparing for programming the STM32F107VC Real Time Clock. fckLR//Define where in the memory the RTC start address peripheral is locatedfckLR#define RTC_BASE 0x40002800 // See reference manual page 52fckLRfckLR//Define the RTC register map. See reference manual section 18.4.7 page 474fckLRunsigned short int volatile * const rtc_crh = (unsigned short int *) RTC_BASE + 0x0;fckLRunsigned short int volatile * const rtc_crl = (unsigned short int *) RTC_BASE + 0x4;fckLRunsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;fckLRfckLR//Initialize the RTC peripheral. See reference manual section 18 page 463fckLRvoid rtc_init(void) {fckLR // Your code herefckLR}fckLR

Initializing the RTC

Goals
Enabling the RTC
One seconds TICK
No interrupts enable
Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
Using external XTAL
Write protect against accidental writes

Enabling the RTC

Power on Init

  1. To enable the RTC it is necessary to enable the Power interface in the RCC->APB1ENR register by setting the PWREN bit to 1. Reference manual section 8.3.8 page 144
  2. To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011Reference manual section 5.4.1 page 75
  3. To enable the Power voltage detector in the PWR->CR register set PVDE to 1.Reference manual section 5.4.1 page 75

Checking if RTC running

  1. In the RCC->BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)Reference manual section 8.3.9 page 146

Programming the RTC

  1. To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR->CR register setting the DBP bit to 1.
  2. To select LSE (Low Speed External XTAL) as clocksource in the RCC->BDCR register bits RTCSEL[1:0] = 01 Reference manual section 8.3.9 page 146
  3. To turn on the LSE in the RCC->BDCR register bit LSEON = 1.Reference manual section 8.3.9 page 146
  4. Wait in while loop (timed out for error check) for the LSE to be ready in RCC->BDCR register bit LSERDY.Reference manual section 8.3.9 page 146
  5. Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC->PRLH = 0 and RTC->PRLL = 0x7fff. Reference manual section 18.4.3 page 470
  6. Setting the Counter to the current time in seconds since epoch. (Set the RTC->CNTH before the RTC->CNTL avoiding RTC->CNTL = 0xffff incrementing RTC->CNTH before writing to it.) Reference manual section 18.4.5 page 472
  7. To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR->CR register setting the DBP bit to 0. Reference manual section 5.4.1 page 75

Links

  • <a _fcknotitle="true" href="Const and volatile type qualifiers">Const and volatile type qualifiers</a>

References

<span class="fck_mw_references" _fck_mw_customtag="true" _fck_mw_tagname="references" />

<a _fcknotitle="true" href="Category:STM32F107VC">STM32F107VC</a> <a _fcknotitle="true" href="Category:ARM">ARM</a>
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