STM32F107VC/GPIO

General Purpose and Alternate Function I/O

Standard GPIO I/O bit

5 volt tolerant GPIO I/O bit

GPIO functional description

Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR).

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes:

• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain
• Output push-pull
• Alternate function push-pull
• Alternate function open-drain

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access.

Default configuration

During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode.

Port Bit Configuration

Each bit can be configured using the configuration registers shown below

GPIO Configuration Registers.

Name	Function
A	A
B	B

Port bit configuration table

Configuration mode		CNF1	CNF0	MODE1	MODE0	PxODR register
General Purpose Output	Push-Pull	0	0	00 01 10		5
	Open Drain	B	C

Detailed description

For detailed description see STM32F107VC Reference Manual Chapter 9.