STM32F107VC/Using the RTC Real Time Clock
Preparing for programming the STM32F107VC Real Time Clock. fckLR//Define where in the memory the RTC start address peripheral is locatedfckLR#define RTC_BASE 0x40002800 // See reference manual page 52fckLRfckLR//Define the RTC register map. See reference manual section 18.4.7 page 474fckLRunsigned short int volatile * const rtc_crh = (unsigned short int *) RTC_BASE + 0x0;fckLRunsigned short int volatile * const rtc_crl = (unsigned short int *) RTC_BASE + 0x4;fckLRunsigned short int volatile * const rtc_prlh = (unsigned short int *) RTC_BASE + 0x8;fckLRfckLR//Initialize the RTC peripheral. See reference manual section 18 page 463fckLRvoid rtc_init(void) {fckLR // Your code herefckLR}fckLR
Contents
Initializing the RTC
- Goals
- Enabling the RTC
- One seconds TICK
- No interrupts enable
- Initializing second counter to present time (Epoch 1/1-1970 00:00:00)
- Using external XTAL
- Write protect against accidental writes
Enabling the RTC
Power on Init
- To enable the RTC it is necessary to enable the Power interface in the RCC->APB1ENR register by setting the PWREN bit to 1. Reference manual section 8.3.8 page 144
- To select the voltage threshold when the RTC switch to battery power. E2PROM minimum operating voltage is 2.5 V. In the PWR->CR register set PLS[2:0] to 011Reference manual section 5.4.1 page 75
- To enable the Power voltage detector in the PWR->CR register set PVDE to 1.Reference manual section 5.4.1 page 75
Checking if RTC running
- In the RCC->BDCR Register check if the RTCEN bit is 1 and the LSEON is 1 and LSERDY is 1 - If not the RTC is not running and need programming. (See below)Reference manual section 8.3.9 page 146
Programming the RTC
- To disable write protection to the Backup domain control register - enabling configuration of the RTC in the PWR->CR register setting the DBP bit to 1.
- To select LSE (Low Speed External XTAL) as clocksource in the RCC->BDCR register bits RTCSEL[1:0] = 01 Reference manual section 8.3.9 page 146
- To turn on the LSE in the RCC->BDCR register bit LSEON = 1.Reference manual section 8.3.9 page 146
- Wait in while loop (timed out for error check) for the LSE to be ready in RCC->BDCR register bit LSERDY.Reference manual section 8.3.9 page 146
- Setting the prescaler of the RTC counter - assuming a 32,768 KHz XTAL - in register RTC->PRLH = 0 and RTC->PRLL = 0x7fff. Reference manual section 18.4.3 page 470
- Setting the Counter to the current time in seconds since epoch. (Set the RTC->CNTH before the RTC->CNTL avoiding RTC->CNTL = 0xffff incrementing RTC->CNTH before writing to it.) Reference manual section 18.4.5 page 472
- To enable write protection to the Backup domain control register - disableing configuration of the RTC in the PWR->CR register setting the DBP bit to 0. Reference manual section 5.4.1 page 75
Links
- <a _fcknotitle="true" href="Const and volatile type qualifiers">Const and volatile type qualifiers</a>
References
<span class="fck_mw_references" _fck_mw_customtag="true" _fck_mw_tagname="references" />
<a _fcknotitle="true" href="Category:STM32F107VC">STM32F107VC</a> <a _fcknotitle="true" href="Category:ARM">ARM</a>