FPGA
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- Teori
- Ole vildledninger???
- Quartus projekt start (Loads PDF file)
- Schamtic & VHDL (Loads PDF file)
- VHDL (Loads PDF file)
- Lkaa vejledning
- Hints
- Installation af driver til DE1 board: Vælg denne sti: C:\altera\91\quartus\drivers\usb-blaster
- Eller hente driver fra Altera's hjemmeside samt instruktion: http://www.altera.com/support/software/drivers/dri-index.html
I have one method of using a counter. The formula for calculating the counter is ( Actual Frequency / required frequency)
use that as the set point for your counter and make use of this code(This IS for 26MHz from 100MHz clock, so the Count value WilL be(100m/26M = 3.)
- if (clock = '1' and clock'event ) then
- if ( count /= 4)
- count := count + 1 ;
- clock_out := clock_out ;
- else
- count := 0 ;
- clock_out := not clock_out ;
- end if;
- end if ;
so for 13MHz the count value will be 7
- Opgaver
- FPGA øvelser (Loads PDF file)
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