STM32F107VC/System architecture

The STM32F107VC is a highly complex device. To understand the device it's necessary first to understand the basic system architecture. Se Chapter 3 in the Reference Manual.

STM32F107VC System Architecture (Click to enlarge)

The STM32F107VC is a connectivity line device with the basic architecture shown to the right.

• Five masters:
  • Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
  • GP-DMA1 & 2 (general-purpose DMA)
  • Ethernet DMA
• Three slaves:
  • Internal SRAM
  • Internal Flash memory
  • AHB to APB bridges (AHB to APBx), which connect all the APB peripherals