STM32F107VC/System architecture
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< STM32F107VC
Revision as of 07:05, 3 September 2011 by Heth (talk | contribs) (Created page with "The STM32F107VC is a highly complex device. To understand the device it's necessary first to understand the basic system architecture. Se Chapter 3 in the [http://www.st.com/...")
The STM32F107VC is a highly complex device. To understand the device it's necessary first to understand the basic system architecture. Se Chapter 3 in the Reference Manual.
The STM32F107VC is a connectivity line device with the basic architecture shown to the right.
- Five masters:
- Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
- GP-DMA1 & 2 (general-purpose DMA)
- Ethernet DMA
- Three slaves:
- Internal SRAM
- Internal Flash memory
- AHB to APB bridges (AHB to APBx), which connect all the APB peripherals